Siemens and Others Discuss New Technologies in the Semiconductor Industry

In a Siemens blog, Karen Chou, Sheetal Veronica, and Kunjesh Agashivala discuss CFET and buried power rails, which reduce chip area and enhance power efficiency for AI, data centers, and mobile processors. Thomas Andersen from Synopsys emphasizes that the best results are achieved when agent AI utilizes the company's specific knowledge: methodologies, project history, priorities, and experience. Rila Samuel from Cadence examines the differences between agent AI and traditional and AI-supported EDA processes, noting that the coordination of operations changes rather than their individual implementation.

Stephen Douglas from Keysight calls for rapid prototyping of the most complex 6G architecture issues. Francisco Socal from Arm presents AMBA C2C, improving chiplet connectivity through AXI and CHI with scalable protocol subsets and support for fully coherent heterogeneous computing. Safi Usmani from SEMI highlights the finalists of the Startups for Sustainable Semiconductors program with solutions ranging from monolithic voltage regulators to wafer defect inspection and GPU-based physics simulation platforms.

Karthik Hegde from Cadence explores a new representation allowing engineers to express intentions more intuitively beyond RTL. Vincent van der Leest from Rambus explains the expanding role of roots of trust in platform security. Brian Davenport from Synopsys discusses a development flow that protects hardware from attacks and leaks. Karthik Sahajpal and Prashant Dixit from Siemens EDA investigate verification in PCIe-over-UCIe systems. Alex Pym from Imagination analyzes time to first token and inter-token latency at prefill and decode stages. Mark Wittman from Keysight notes that trade restrictions now concern not the place of manufacture but how the product operates. Separately, Karthik Rangarajan from Infineon demonstrates how distributed non-volatile memory supports telemetry, functional safety, and time-sensitive networks.